a.k.a. Single-Writer-Multiple-Reader
缓存一致性协议的一种性质，CPU所使用的常见协议都具有该性质。
Their defining characteristic is that a write to a memory location eagerly invalidates all other cached copies, ensuring there is only ever one writer; there can, however, be multiple readers that can concurrently read cached locations. Compound Memory Models
Another way to view this definition is to consider, for each memory location, that the memory location’s lifetime is divided up into epochs. In each epoch, either a single core has read-write access or some number of cores (possibly zero) have read-only access. A Primer on Memory Consistency and Cache Coherence
另一种基于令牌的的定义方式：
The invariants are as follows. For each memory location, there exists a fixed number of tokens that is at least as large as the number of cores. If a core has all of the tokens, it may write the memory location. If a core has one or more tokens, it may read the memory location. At any given time, it is thus impossible for one core to be writing the memory location while any other core is reading or writing it. A Primer on Memory Consistency and Cache Coherence