CXL 3.0 标准引入HDM-DB，通过Back-invalidation来实现多主机之间的缓存一致。但是这需要主机侧也支持这项特性。
在当下的结论是：暂且没有实现，可以通过软件实现主机间缓存一致性；如果只是模拟的话，现在的模拟器应该也支持。部分应用也被设计为可以在没有硬件支持的缓存一直性下工作。
业界动向
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2025 阿里巴巴与XConn合作的工作PolarCXLMem发表 其中已有Memory Sharing的落地；此前也有类似的工作。不过这其中的主机间缓存一致性是软件实现的。
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2026-03-17 Marvell 发布通告，在OFC 2026展示Structera S系列CXL交换机。博客见：Structera S: Scaling the AI Memory Wall with CXL Switching，另见媒体通告Marvell Launches Next-generation CXL Switch, Enabling Memory Pooling to Break Through the AI “Memory Wall”
其中有提到上述工作，隐含支持sharing的意思仔细看了一下，官方通稿只在强调内存池化，如果实现了共享不可能不宣传的。Structera S 30260 features support for 16 or 32 CPUs or GPUs over 260 lanes with up to 48TB of shared memory and 4TB/second cumulative bandwidth. Marvell is showcasing Structera S 30260 in a live demonstration this week at OFC 2026 and plans on sampling to customers in 3Q 2026.
The Marvell Structera S 30260 CXL switch is expected to begin sampling to customers in calendar Q3 2026. The Structera S 20256 CXL 2.0 switch is currently in production.
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澜起科技的CXL 3.1实现：M88MX6852 | Montage Technology
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Panmnesic 支持PBR：Panmnesia Showcases PCIe 6.4 / CXL 3.2 Fabric Switch and Pilot System at CES 2026
学界
- ASPLOS26: “Currently, there is no CPU or pool device that implements CXL 3.0 back invalidation flows, so cache-coherent sharing is unavailable [77]. Therefore, we distinguish between a non-coherent, realistic memory pool and a cachecoherent pool envisioned according to the specification.” (Lahav) 实际硬件已经支持PBR，但是是否实现了back-invalidation（BI）则是未知的
- 去年的HotOS文章则直接说明了BI尚且没有CPU和Device实现（需要两者配合）
“However, implementing BI involves both processorside and device-side changes, which greatly increases hardware complexity and costs. Neither CPUs nor CXL memory pool devices support BI today.”
- ASPLOS26, CXLALLOC: “but given implementation cost and complexity, it is unclear if HWcc will become widely supported in practice.” 其中也提到目前学界研究时要么假设有HWcc，要么需要自行在软件层面实现多主机之间的缓存一致（比如PolarDB和Tigon这两个数据库都是这样）